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DESCRIPTION
The WM8521 is a 192kHz stereo DAC with an integrated output op-amp stage, designed to generate a 2.0Vrms output signal directly, so reducing external component requirements in digital audio applications. WM8521 comes into two variants WM8521HC and WM8521H9 which offers different line drive output capabilities. WM8521HC outputs 2Vrms at 12V supply, while WM8521H9 outputs 2.0Vrms at 9V supply. WM8521HC/H9 are designed for cost sensitive consumer digital audio applications requiring 2Vrms line output. A 24-bit multi-bit sigma delta DAC is used with oversampling digital interpolation filters. Digital audio input word lengths from 16-32 bits and sampling rates from 8kHz to 192kHz are supported. The audio interface supports I S, Right Justified and DSP digital audio formats. The devices are controlled via a hardware interface which provides access to features including de-emphasis, mute and data formats. These devices are pin equivalent and are available in a 14-lead SOIC package.
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WM8521
Stereo DAC with Integrated Output Stage for 2Vrms LINE OUT
FEATURES
* * * * * * Audio Performance - DAC SNR 98dB (`A' weighted @ 48kHz) - THD -81dB (`A' weighted @ 48kHz) DAC Sampling Frequency: 8kHz - 192kHz Pin Selectable Audio Data Interface Format - I2S, 16-bit Right Justified or 16bit DSP 2.0 Vrms output at 12V or 9V supply 7.6V to 13.2V Analogue, 2.7V to 3.6 Digital Supply 14-lead SOIC Package
APPLICATIONS
* Consumer digital audio applications requiring 2 Vrms output - DVD Players - Digital TV - Digital Set Top Boxes - A/V Receivers
BLOCK DIAGRAM
WOLFSON MICROELECTRONICS plc
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Production Data, August 2006, Rev 4.1 Copyright 2006 Wolfson Microelectronics plc
WM8521 TABLE OF CONTENTS
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DESCRIPTION .......................................................................................................1 FEATURES.............................................................................................................1 APPLICATIONS .....................................................................................................1 BLOCK DIAGRAM .................................................................................................1 TABLE OF CONTENTS .........................................................................................2 PIN CONFIGURATION...........................................................................................3 ORDERING INFORMATION ..................................................................................3 PIN DESCRIPTION ................................................................................................4 ABSOLUTE MAXIMUM RATINGS.........................................................................5 DC ELECTRICAL CHARACTERISTICS ................................................................6 ELECTRICAL CHARACTERISTICS ......................................................................6
TERMINOLOGY............................................................................................................. 7 MASTER CLOCK TIMING.............................................................................................. 8 DIGITAL AUDIO INTERFACE........................................................................................ 8
DEVICE DESCRIPTION.........................................................................................9
GENERAL INTRODUCTION.......................................................................................... 9 DAC CIRCUIT DESCRIPTION....................................................................................... 9 CLOCKING SCHEMES ................................................................................................ 10 DIGITAL AUDIO INTERFACE...................................................................................... 10 AUDIO DATA SAMPLING RATES ............................................................................... 12 HARDWARE CONTROL MODES................................................................................ 13 DIGITAL FILTER CHARACTERISTICS ....................................................................... 15 DAC FILTER RESPONSES ......................................................................................... 15 DIGITAL DE-EMPHASIS CHARACTERISTICS ........................................................... 16
APPLICATIONS INFORMATION .........................................................................17
RECOMMENDED EXTERNAL COMPONENTS........................................................... 17 RECOMMENDED EXTERNAL COMPONENTS VALUES............................................ 17 RECOMMENDED ANALOGUE LOW PASS FILTER ................................................... 18 PCB LAYOUT RECOMMENDATIONS......................................................................... 18
PACKAGE DRAWING..........................................................................................19 IMPORTANT NOTICE ..........................................................................................20
ADDRESS:................................................................................................................... 20
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WM8521
PIN CONFIGURATION
ORDERING INFORMATION
DEVICE WM8521HCGED/V WM8521HCGED/RV TEMPERATURE RANGE -25 to +85oC -25 to +85oC PACKAGE 14-lead SOIC (Pb- free) 14-lead SOIC (Pb-free, tape and reel) 14-lead SOIC (Pb-free) 14-lead SOIC (Pb-free, tape and reel) MOISTURE SENSITIVITY LEVEL MSL1 MSL1 PEAK SOLDERING TEMPERATURE 260oC 260oC
WM8521H9GED/V WM8521H9GED/RV
-25 to +85oC -25 to +85 C
o
MSL1 MSL1
260oC 260oC
Note: 1. 2. 3. Reel quantity = 3,000 WM8521H9: 2Vrms output at 9V supply WM8521HC: 2Vrms output at 12V supply
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WM8521 PIN DESCRIPTION
PIN 1 2 3 4 5 NAME DGND LRCLK DIN BCLK MUTE Supply Digital input Digital input Digital input Digital input TYPE Digital Negative supply Sample rate clock input Serial audio data input Bit clock input Soft mute control, Internal pull down High Impedance = Automute High = Mute ON Low = Mute OFF Right channel DAC output Analogue Negative supply Analogue internal reference Analogue Positive supply Left channel DAC output De-emphasis select, Internal pull down High = de-emphasis ON Low = de-emphasis OFF Data input format select, Internal pull up Low = 16-bit right justified or 16bit DSP `Mode A' High = 16-32-bit I2S or 16bit DSP `Mode B' Master clock input Digital Positive supply DESCRIPTION
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6 7 8 9 10 11
VOUTR AGND CAP AVDD VOUTL DEEMPH
Analogue output Supply Analogue output Supply Analogue output Digital input
12
FORMAT
Digital input
13 14 Note: 1.
MCLK DVDD
Digital input Supply
Digital input pins have Schmitt trigger input buffers.
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WM8521
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics at the test conditions specified. ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this device. Wolfson tests its package types according to IPC/JEDEC J-STD-020B for Moisture Sensitivity to determine acceptable storage conditions prior to surface mount assembly. These levels are: MSL1 = unlimited floor life at <30C / 85% Relative Humidity. Not normally stored in moisture barrier bag. MSL2 = out of bag storage for 1 year at <30C / 60% Relative Humidity. Supplied in moisture barrier bag. MSL3 = out of bag storage for 168 hours at <30C / 60% Relative Humidity. Supplied in moisture barrier bag. The Moisture Sensitivity Level for each package type is specified in Ordering Information. Supplies are independent and can be applied in either order without damage to device. CONDITION Analogue Supply Voltage (AVDD) Digital Supply voltage (DVDD) Voltage range digital inputs Master Clock Frequency Operating temperature range, TA Storage temperature prior to soldering Storage temperature after soldering -25C MIN -0.3V -0.3V DGND -0.3V MAX +15V +4.2V DVDD +0.3V 50MHz +85C
30C max / 85% RH max -65C +150C
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WM8521 DC ELECTRICAL CHARACTERISTICS
PARAMETER WM8521HC Analogue supply range WM8521H9 Analogue supply range Digital supply range Ground WM8521HC Supply current WM8521H9 Supply current WM8521HC Power down current (note 4) WM8521H9 Power down current (note 4) Note: 1. AVDD and DVDD are fully independent and can be applied in any order without damage to the device. SYMBOL AVDD AVDD DVDD AGND / DGND IAVDD IDVDD IAVDD IDVDD IAVDD IDVDD IAVDD IDVDD AVDD = 12V DVDD = 3.3V AVDD = 9V DVDD = 3.3V AVDD = 12V DVDD = 3.3V AVDD = 9V DVDD = 3.3V TEST CONDITIONS MIN 7.6 7.6 2.7 TYP 12 9 3.3 0 28.0 4.0 25.0 4.0 22.8 0.014 17.1 0.014 MAX 13.2 13.2 3.6
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UNIT V V V V mA mA mA mA
ELECTRICAL CHARACTERISTICS
Test Conditions WM8521HC: AVDD = 12V, DVDD = 3.3V, AGND / DGND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs unless otherwise stated. WM8521H9: AVDD = 9V, DVDD = 3.3V, AGND / DGND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs unless otherwise stated. PARAMETER Input LOW level Input HIGH level Output LOW Output HIGH Analogue Reference Levels Reference voltage (CAP) Potential divider resistance RCAP VDD to CAP and CAP to GND At DAC outputs A-weighted, @ fs = 48kHz A-weighted @ fs = 96kHz Non `A' weighted @ fs = 48kHz 1kHz, 0dBFs 1kHz, THD+N @ -60dBFs 1kHz, 0dBFs PSRR 1kHz 100mVpp 91 1.9 91 AVDD/2 50 V k SYMBOL VIL VIH VOL VOH IOL = 1mA IOH = -1mA 0.9 x DVDD 0.7 x DVDD 0.1 x DVDD TEST CONDITIONS MIN TYP MAX 0.3 x DVDD UNIT V V V V Digital Logic Levels (CMOS Levels)
WM8521HC DAC Output (Load = 10k. 50pF) 0dBFs Full scale output voltage SNR (Terminology Note 1,2,3) SNR (Terminology Note 1,2,3) SNR (Terminology Note 1,2,3) THD (Note 3) Dynamic Range (Note 2) DAC Channel Separation Power Supply Rejection Ratio 2.0 98 98 95 -81 98 93 46 2.1 Vrms dB dB dB dB dB dB dB
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WM8521
Test Conditions o WM8521HC: AVDD = 12V, DVDD = 3.3V, AGND / DGND = 0V, TA = +25 C, fs = 48kHz, MCLK = 256fs unless otherwise stated. WM8521H9: AVDD = 9V, DVDD = 3.3V, AGND / DGND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs unless otherwise stated. PARAMETER 0dBFs Full scale output voltage SNR (Terminology Note 1,2,3) SNR (Terminology Note 1,2,3) SNR (Terminology Note 1,2,3) THD (Note 3) Dynamic Range (Note 2) DAC Channel Separation Power Supply Rejection Ratio Analogue Output Levels Gain Mismatch Channel-to-channel Minimum Resistance Load Maximum Capacitance Load Output d.c. Level Power On Reset (POR) POR Threshold Notes: 1. 2. Ratio of output level with 1kHz full scale input, to the output level with all zeros into the digital input, measured `A' weighted over a 20Hz to 20kHz bandwidth. All performance measurements done with 20kHz low pass filter, and where noted an A-weight filter. Failure to use such a filter will result in higher THD+N and lower SNR and Dynamic Range readings than are found in the Electrical Characteristics. The low pass filter removes out of band noise; although it is not audible it may affect dynamic specification values. CAP pin decoupled with 10uF and 0.1uF capacitors (smaller values may result in reduced performance). Power down refers to operation after MCLK has been stopped. Digital reset occurs 1.5s after MCLK is stopped. DVDD 1.56 V AVDD/2 To midrail or a.c. coupled 1 5 5.6 %FSR k nF V PSRR SYMBOL TEST CONDITIONS At DAC outputs A-weighted, @ fs = 48kHz A-weighted @ fs = 96kHz Non `A' weighted @ fs = 48kHz 1kHz, 0dBFs 1kHz, THD+N @ -60dBFs 1kHz, 0dBFs 1kHz 100mVpp 91 MIN 1.9 91 TYP 2.0 96 96 93 -81 96 93 46 MAX 2.1 UNIT Vrms dB dB dB dB dB dB dB WM8521H9 DAC Output (Load = 10k. 50pF)
3. 4.
TERMINOLOGY
1. Signal-to-noise ratio (dB) - SNR is a measure of the difference in level between the full scale output and the output with no signal applied. (No Auto-zero or Automute function is employed in achieving these results). Dynamic range (dB) - DNR is a measure of the difference between the highest and lowest portions of a signal. Normally a THD+N measurement at 60dB below full scale. The measured signal is then corrected by adding the 60dB to it. (e.g. THD+N @ -60dB= -32dB, DR= 92dB). THD+N (dB) - THD+N is a ratio, of the rms values, of (Noise + Distortion)/Signal. Stop band attenuation (dB) - Is the degree to which the frequency spectrum is attenuated (outside audio band). Channel Separation (dB) - Also known as Cross-Talk. This is a measure of the amount one channel is isolated from the other. Normally measured by sending a full scale signal down one channel and measuring the other.
2.
3. 4. 5.
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WM8521
MASTER CLOCK TIMING
tMCLKL MCLK tMCLKH tMCLKY
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Figure 1 Master Clock Timing Requirements
Test Conditions AVDD = 12V, DVDD = 3.3V, AGND / DGND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs unless otherwise stated. PARAMETER System Clock Timing Information MCLK Master clock pulse width high MCLK Master clock pulse width low MCLK Master clock cycle time MCLK Duty cycle Time from MCLK stopping to digital reset tMCLKH tMCLKL tMCLKY 11 11 28 40:60 1.5 60:40 12 s ns ns ns SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
DIGITAL AUDIO INTERFACE
BCH BCLK BCY LRCLK DS DIN DH Figure 2 Digital Audio Data Timing Test Conditions AVDD = 12V, DVDD = 3.3V, AGND / DGND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs unless otherwise stated. PARAMETER BCLK cycle time BCLK pulse width high BCLK pulse width low LRCLK set-up time to BCLK rising edge LRCLK hold time from BCLK rising edge DIN set-up time to BCLK rising edge DIN hold time from BCLK rising edge SYMBOL tBCY tBCH tBCL tLRSU tLRH tDS tDH TEST CONDITIONS MIN 50 20 20 10 10 10 10 TYP MAX UNIT ns ns ns ns ns ns ns Audio Data Input Timing Information LRH LRSU BCL
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WM8521
DEVICE DESCRIPTION
GENERAL INTRODUCTION
The WM8521 is a high performance DAC designed for digital consumer audio applications requiring a 2Vrms output. The range of features make it ideally suited for use in DVD players, Digital TV, Digital Set Top Boxes, AV receivers and other consumer audio equipment. The WM8521 is a complete 2-channel stereo audio digital-to-analogue converter, including digital interpolation filter, multi-bit sigma delta with dither, switched capacitor multi-bit stereo DAC and output smoothing filters combined with 2Vrms outputs. It is fully compatible and an ideal partner for a range of industry standard microprocessors, controllers and DSPs. A novel multi bit sigma-delta DAC design is used, utilising a 128x oversampling rate, to optimise signal to noise performance and offer increased clock jitter tolerance. Control of internal functionality of the device is provided by hardware control (pin programmed). Operation using master clocks of 256fs, 384fs, 512fs or 768fs is provided, selection between clock rates being automatically controlled. Sample rates (fs) from 8kHz to 192kHz are allowed provided the appropriate system clock is input. The audio data interface supports 16-bit right justified or 16-, 20-, 24-, 32-bit I2S interface formats. A 16bit DSP interface is also supported, enhancing the interface options for the user. The device is packaged in a small 14-pin SOIC.
DAC CIRCUIT DESCRIPTION
The WM8521 DAC is designed to allow playback of 24-bit PCM audio or similar data with high resolution and low noise and distortion. Sample rates from 8kHz to 192kHz may be used provided that the ratio of sample rate (LRCLK) to master clock (MCLK) is maintained at one of the required rates. The two DACs on the WM8521 are implemented using sigma-delta oversampled conversion techniques. These require that the PCM samples are digitally filtered and interpolated to generate a set of samples at a much higher rate than the input rate. This sample stream is then digitally modulated to generate a digital pulse stream that is then converted to analogue signals in a switched capacitor DAC. The advantage of this technique is that the DAC is linearised using noise shaping techniques, allowing the 24-bit resolution to be met using non-critical analogue components. A further advantage is that the high sample rate at the DAC output means that smoothing filters on the output of the DAC need only have fairly crude characteristics in order to remove the characteristic steps, or images on the output of the DAC. To ensure that generation of tones characteristic to sigma-delta convertors is not a problem, dithering is used in the digital modulator along with a higher order modulator. The multi-bit switched capacitor technique used in the DAC reduces sensitivity to clock jitter, and dramatically reduces out of band noise compared to switched current or single bit techniques used in other implementations. The voltage on the CAP pin is used as the reference for the DACs. Therefore the amplitude of the signals at the DAC outputs will scale with the amplitude of the voltage at the CAP pin. An external reference could be used to drive into the CAP pin if desired, with a value typically of about midrail ideal for optimum performance. However driven in normal operation, an internal divider will set a valve of AVDD/2 on the cap pin. Typically an external low pass filter circuit will be used to remove residual out of band noise characteristic of delta sigma converters. However, the advanced multi-bit DAC used in WM8521 produces far less out of band noise than single bit traditional sigma delta DACs, and so in many applications this filter may be removed, or replaced with a simple RC pole.
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CLOCKING SCHEMES
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In a typical digital audio system there is only one central clock source producing a reference clock to which all audio data processing is synchronised. This clock is often referred to as the audio system's Master Clock. The external master clock can be applied directly through the MCLK input pin with no configuration necessary for sample rate selection. Note that on the WM8521, MCLK is used to derive clocks for the DAC path. The DAC path is affected by DAC sampling clock, DAC digital filter clock and DAC digital audio interface timing. In a system where there are a number of possible sources for the reference clock it is recommended that the clock source with the lowest jitter be used to optimise the performance of the DAC. The device can be reset by stopping MCLK. In this state the power consumption is substantially reduced.
DIGITAL AUDIO INTERFACE
Audio data is applied to the internal DAC filters via the Digital Audio Interface. Three interface formats are supported: * I2S mode * Right Justified mode * DSP mode All formats send the MSB first. The data format is selected with the FORMAT pin. When FORMAT is LOW, right justified data format is selected and word lengths up to 16-bits may be used. If a word length shorter than 16-bits is used, the unused bits should be padded with zeroes. When the FORMAT pin is HIGH, I2S format is selected and word length of any value up to 32-bits may be used. Unless in 16-bit `packed' mode, if a word length shorter than 24-bits is used, the unused bits should be padded with zeros. If LRCLK is 4 BCLKs or less duration, the 16bit DSP compatible format is selected. Mode A and B clock formats are supported, selected by the state of the FORMAT pin.
I S MODE INPUT FORMAT
The WM8521 supports word lengths of 16-32 bits in I2S mode. In I2S mode, the digital audio interface receives data on the DIN input. Audio Data is time multiplexed with LRCLK indicating whether the left or right channel is present. LRCLK is also used as a timing reference to indicate the beginning or end of the data words. 25-32 bits: LRCLK must be high for a minimum of data wordlength BCLKs and low for a minimum of data wordlength BCLKs. The LSBs will be truncated and the most significant 24 bits will be used by the internal processing. 24 bits: LRCLK must be high for a minimum of 24 BCLKs and low for a minimum of 24 BCLKs. 17-23 bits: Data must be zero padded to 24 bits and LRCLK must be high for a minimum of 24 BCLKs and low for a minimum of 24 BCLKs. Up to 16 bits: EITHER data must be zero padded to 24 bits and LRCLK must be high for minimum 24 BCLKs and low for 24 BCLKs, OR data must be zero padded to 16 bits and LRCLK must be high for exactly 16 BCLKs and low for exactly 16 BCLKs. The device auto-detects this '16-bit packed' mode and switches to 16-bit data length. Any mark to space ratio on LRCLK is acceptable provided the above requirements are met.
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WM8521
In I2S mode, the MSB is sampled on the second rising edge of BCLK following a LRCLK transition. LRCLK is low during the left samples and high during the right samples.
1/fs LEFT CHANNEL LRCLK RIGHT CHANNEL
BCLK 1 BCLK DIN 1 MSB 2 3 n-2 n-1 n LSB 1 BCLK 1 MSB 2 3 n-2 n-1 n LSB
Figure 3 I2S Mode Timing Diagram
RIGHT JUSTIFIED MODE INPUT FORMAT
The WM8521 supports word lengths of up to 16-bits in right justified mode. If a word length shorter than 16-bits is used, the unused bits should be padded with zeroes. In right justified mode, LRCLK must be high for a minimum of 16 BCLKs and low for a minimum of 16 BCLKs. Any mark to space ratio on LRCLK is acceptable provided the above requirement is met. The digital audio interface receives data on the DIN input. Audio Data is time multiplexed with LRCLK indicating whether the left or right channel is present. LRCLK is also used as a timing reference to indicate the beginning or end of the data words. In right justified mode, the LSB is sampled on the rising edge of BCLK preceding a LRCLK transition. LRCLK is high during the left samples and low during the right samples.
1/fs LEFT CHANNEL LRCLK RIGHT CHANNEL
BCLK
DIN
1 MSB
2
3
14 15 16 LSB
1 MSB
2
3
14 15 16 LSB
Figure 4 Right Justified Mode Timing Diagram
DSP MODE INPUT FORMAT
A DSP compatible, time division multiplexed format is also supported by the WM8521. This format is of the type where a `synch' pulse is followed by two data words (left and right) of 16 bit word length. The `synch' pulse replaces the normal duration LRCLK, and DSP mode is auto-detected by the shorter than normal duration of the LRCLK. If LRCLK is of 4 BCLK or less duration, the DSP compatible format is selected. Mode A and Mode B formats are supported, selected by the state of the FORMAT pin.
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1/fs Max 4 BCLKs LRCLK
BCLK LEFT CHANNEL DIN 1 MSB 2 15 16 LSB 1 2 RIGHT CHANNEL 15 16 NO VALID DATA 1 MSB
Input Word Length (16 bits)
Figure 5 DSP Timing Mode B
1 BCLK 1/fs Max 4 BCLKs LRCLK 1 BCLK
BCLK LEFT CHANNEL DIN 1 MSB 2 15 16 LSB 1 RIGHT CHANNEL 2 15 16 NO VALID DATA
Input Word Length (16 bits)
Figure 6 DSP Timing Mode A
AUDIO DATA SAMPLING RATES
The master clock for WM8521 supports audio sampling rates from 256fs to 768fs, where fs is the audio sampling frequency (LRCLK) typically 32kHz, 44.1kHz, 48kHz, 96kHz or 192kHz. The master clock is used to operate the digital filters and the noise shaping circuits. The WM8521 has a master clock detection circuit that automatically determines the relationship between the master clock frequency and the sampling rate (to within +/- 32 master clocks). If there is a greater than 32 clocks error, the master clock defaults to 768fs. The master clock should be synchronised with LRCLK, although the WM8521 is tolerant of phase differences or jitter on this clock. SAMPLING RATE (LRCLK) 32kHz 44.1kHz 48kHz 96kHz 192kHz MASTER CLOCK FREQUENCY (MHz) (MCLK) 128fs 4.096 5.6448 6.144 12.288 24.576 192fs 6.144 8.467 9.216 18.432 36.864 256fs 8.192 11.2896 12.288 24.576 Unavailable 384fs 12.288 16.9344 18.432 36.864 Unavailable 512fs 16.384 22.5792 24.576 Unavailable Unavailable 768fs 24.576 33.8688 36.864 Unavailable Unavailable
Table 1 Master Clock Frequencies Versus Sampling Rate Note: For sample rates down to 8k, scale MCLK accordingly.
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WM8521
HARDWARE CONTROL MODES
The WM8521 is hardware programmable providing the user with options to select input audio data format, de-emphasis and mute.
MUTE AND AUTO MUTE OPERATION
Pin 5 (MUTE) controls the mute function, or can be used as an output to monitor the state of the automuted signal. MUTE PIN 0 1 Floating Normal Operation, MUTE off Mute DAC channels Enable IZD, MUTE becomes an output to indicate when IZD occurs. DESCRIPTION
Table 2 Mute and Automute Control
1.5 1 0.5 0 -0.5 -1 -1.5 -2 -2.5 0 0.001 0.002 0.003 Time(s) 0.004 0.005 0.006
Figure 7 Application and Release of MUTE MUTE is active high; taking the pin high causes the filters to soft mute, ramping down the audio signal over a few milliseconds. Taking MUTE low again allows data into the filter. Refer to Figure 7. Therefore if MUTE is tied low then mute is disabled and the automute function is overridden. If MUTE is floating or connected to a high impedance then the automute function will operate. The AUTOMUTED internal signal, which is generated by the IZD function, is connected to the MUTE pin internally via a 10k resistor. This can provide a weak output (10k source impedance) which can be used to drive external mute circuits. Refer to Figure 8. The Infinite Zero Detect (IZD) function detects 1024 zero value audio samples applied to both channels. After such an event, a latch is set whose output is the AUTOMUTED internal signal. AUTOMUTED will be reset as soon as either channel receives a non-zero input.
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A diagram showing how the various Mute modes interact is shown below in Figure 8.
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AUTOMUTED (Internal Signal) 10k MUTE PIN SOFTMUTE (Internal Signal)
Figure 8 Selection Logic for MUTE Modes
INPUT AUDIO FORMAT SELECTION
FORMAT (pin 12) controls the data input format. FORMAT 0 1 Table 3 Input Audio Format Selection INPUT DATA MODE 16 bit right justified 16-32 bit I2S
INPUT DSP FORMAT SELECTION
FORMAT 0 1 LRCLK DATAWIDTH BCLKS LRCLK OF 4 BCLK OR LESS DURATION 16 bit DSP format - Mode A 16 bit DSP format - Mode B 16 bit (MSB-first, right justified) I2S format up to 24 bit
Table 4 DSP Interface Formats
DE-EMPHASIS CONTROL
DEEMPH (pin 11) is an input control for selection of de-emphasis filtering to be applied. DEEMPH 0 1 Table 5 De-emphasis Control DE-EMPHASIS Off On
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SYMBOL TEST CONDITIONS -3dB f < 0.444fs f > 0.555fs -60 28 MIN TYP 0.487fs 0.1 dB dB fs MAX UNIT
DIGITAL FILTER CHARACTERISTICS
PARAMETER Passband Edge Passband Ripple Stopband Attenuation Group Delay Table 6 Digital Filter Characteristics
DAC FILTER RESPONSES
10
0 -20 Response (dB) -40 -60 -80 -100 -120 0 0.5 1 1.5 2 2.5 3 Frequency (Fs)
Response (dB)
0 -10 -20 -30 -40 -50 -60 -70 -80 0.4 0.45 0.5 Frequency (Fs) 0.55 0.6
Figure 9 DAC Digital Filter Frequency Response -44.1,48 and 96kHz
Figure 10 DAC Digital Filter Transition Band -44.1,48 and 96kHz
0.2 0.15 0.1 Response (dB) 0.05 0 -0.05 -0.1 -0.15 -0.2 0 0.1 0.2 Frequency (Fs) 0.3 0.4 0.5
Figure 11 DAC Digital Filter Ripple - 44.1, 48 and 96kHz
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DIGITAL DE-EMPHASIS CHARACTERISTICS
0 1 0.5 -2 0
Response (dB)
Response (dB)
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-4
-0.5 -1 -1.5 -2
-6
-8 -2.5 -10 0 2 4 6 8 10 Frequency (kHz) 12 14 16 -3 0 2 4 6 8 10 Frequency (kHz) 12 14 16
Figure 12 De-Emphasis Frequency Response (32kHz)
0
Figure 13 De-Emphasis Error (32KHz)
0.4 0.3
-2 0.2
Response (dB)
Response (dB)
-4
0.1 0 -0.1 -0.2
-6
-8 -0.3 -10 0 5 10 Frequency (kHz) 15 20 -0.4 0 5 10 Frequency (kHz) 15 20
Figure 14 De-Emphasis Frequency Response (44.1KHz)
0
Figure 15 De-Emphasis Error (44.1KHz)
1 0.8
-2
0.6 0.4
Response (dB)
-4
Response (dB)
0.2 0 -0.2 -0.4
-6
-8
-0.6 -0.8
-10 0 5 10 15 Frequency (kHz) 20
-1 0 5 10 15 Frequency (kHz) 20
Figure 16 De-Emphasis Frequency Response (48kHz)
Figure 17 De-Emphasis Error (48kHz)
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APPLICATIONS INFORMATION
RECOMMENDED EXTERNAL COMPONENTS
Figure 18 Recommended External Components
RECOMMENDED EXTERNAL COMPONENTS VALUES
COMPONENT REFERENCE C1 C2 C3 C4 C5 and C6 C7 C8 SUGGESTED VALUE 10F 0.1F 10F 0.1F 10F 0.1F 10F De-coupling for AVDD De-coupling for AVDD De-coupling for DVDD De-coupling for DVDD Output AC coupling caps to remove midrail DC level from outputs Reference de-coupling capacitors for CAP pin DESCRIPTION
Table 7 External Components Description
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RECOMMENDED ANALOGUE LOW PASS FILTER
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Figure 19 Recommended 1st Order Low Pass Filter Note: Capacitors should be COG dielectric.
An external single pole RC filter is recommended (see Figure 19) if the device is driving a wideband amplifier. However the WM8521 does contain an internal low pass filter which should be adequate in most applications.
PCB LAYOUT RECOMMENDATIONS
Care should be taken in the layout of the PCB that the WM8521 is to be mounted to. The following notes will help in this respect: The VDD supply to the device should be as noise free as possible. This can be accomplished to a large degree with a 10uF bulk capacitor placed locally to the device and a 0.1uF high frequency decoupling capacitor placed as close to the VDD pin as possible. It is best to place the 0.1uF capacitor directly between the VDD and GND pins of the device on the same layer to minimize track inductance and thus improve device decoupling effectiveness. The CAP pin should be as noise free as possible. This pin provides the decoupling for the on chip reference circuits and thus any noise present on this pin will be directly coupled to the device outputs. In a similar manner to the VDD decoupling described above, this pin should be decoupled with a 10uF bulk capacitor local to the device and a 0.1uF capacitor as close to the CAP pin as possible. Separate analogue and digital track routing from each other. The device is split into analogue (pins 5 - 10) and digital (pins 1 - 4 & pins 11 - 14) sections that allow the routing of these signals to be easily separated. By physically separating analogue and digital signals, crosstalk from the PCB can be minimized. Use an unbroken solid GND plane. To achieve best performance from the device, it is advisable to have either a GND plane layer on a multilayer PCB or to dedicate one side of a 2 layer PCB to be a GND plane. For double sided implementations it is best to route as many signals as possible on the device mounted side of the board, with the opposite side acting as a GND plane. The use of a GND plane greatly reduces any electrical emissions from the PCB and minimizes crosstalk between signals. An evaluation board is available for the WM8521 that demonstrates the above techniques and the excellent performance achievable from the device. This can be ordered or the User manual downloaded from the Wolfson web site at www.wolfsonmicro.com
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Production Data
WM8521
PACKAGE DRAWING
D: 14 PIN SOIC 3.9mm Wide Body DM001.C
e
B
14
8
H E
1
7
D
L h x 45o
A1 -CA
SEATING PLANE
C
0.10 (0.004)
Symbols A A1 B C D E e H h L REF:
Dimensions (mm) MIN MAX 1.35 1.75 0.10 0.25 0.33 0.51 0.19 0.25 8.55 8.75 3.80 4.00 1.27 BSC 5.80 6.20 0.25 0.50 0.40 1.27 o o 0 8 JEDEC.95, MS-012
Dimensions (Inches) MIN MAX 0.0532 0.0688 0.0040 0.0098 0.0130 0.0200 0.0075 0.0098 0.3367 0.3444 0.1497 0.1574 0.05 BSC 0.2284 0.2440 0.0099 0.0196 0.0160 0.0500 o o 0 8
NOTES: A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS (INCHES). B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE. C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.25MM (0.010IN). D. MEETS JEDEC.95 MS-012, VARIATION = AB. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS.
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WM8521 IMPORTANT NOTICE
Production Data
Wolfson Microelectronics plc ("Wolfson") products and services are sold subject to Wolfson's terms and conditions of sale, delivery and payment supplied at the time of order acknowledgement.
Wolfson warrants performance of its products to the specifications in effect at the date of shipment. Wolfson reserves the right to make changes to its products and specifications or to discontinue any product or service without notice. Customers should therefore obtain the latest version of relevant information from Wolfson to verify that the information is current.
Testing and other quality control techniques are utilised to the extent Wolfson deems necessary to support its warranty. Specific testing of all parameters of each device is not necessarily performed unless required by law or regulation.
In order to minimise risks associated with customer applications, the customer must use adequate design and operating safeguards to minimise inherent or procedural hazards. Wolfson is not liable for applications assistance or customer product design. The customer is solely responsible for its selection and use of Wolfson products. Wolfson is not liable for such selection or use nor for use of any circuitry other than circuitry entirely embodied in a Wolfson product.
Wolfson's products are not intended for use in life support systems, appliances, nuclear systems or systems where malfunction can reasonably be expected to result in personal injury, death or severe property or environmental damage. Any use of products by the customer for such purposes is at the customer's own risk.
Wolfson does not grant any licence (express or implied) under any patent right, copyright, mask work right or other intellectual property right of Wolfson covering or relating to any combination, machine, or process in which its products or services might be or are used. Any provision or publication of any third party's products or services does not constitute Wolfson's approval, licence, warranty or endorsement thereof. Any third party trade marks contained in this document belong to the respective third party owner.
Reproduction of information from Wolfson datasheets is permissible only if reproduction is without alteration and is accompanied by all associated copyright, proprietary and other notices (including this notice) and conditions. Wolfson is not liable for any unauthorised alteration of such information or for any reliance placed thereon.
Any representations made, warranties given, and/or liabilities accepted by any person which differ from those contained in this datasheet or in Wolfson's standard terms and conditions of sale, delivery and payment are made, given and/or accepted at that person's own risk. Wolfson is not liable for any such representations, warranties or liabilities or for any reliance placed thereon by any person.
ADDRESS:
Wolfson Microelectronics plc Westfield House 26 Westfield Road Edinburgh EH11 2QB United Kingdom Tel :: +44 (0)131 272 7000 Fax :: +44 (0)131 272 7001 Email :: sales@wolfsonmicro.com
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